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DG444, DG445
Data Sheet June 4, 2007 FN3586.10
Monolithic, Quad SPST, CMOS Analog Switches
The DG444 and DG445 monolithic CMOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole single throw (SPST) analog switches and TTL and CMOS compatible digital inputs. These switches feature lower analog ON resistance (<85) and faster switch time (tON <250ns) compared to the DG211 and DG212. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG444 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 20V signals when operating with 20V power supplies. The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a 5V analog input range. The switches in the DG444 and DG445 are identical, differing only in the polarity of the selection logic.
Features
* ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 85 * Low Power Consumption (PD) . . . . . . . . . . . . . . . <35W * Fast Switching Action - tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns - tOFF (Max, DG444) . . . . . . . . . . . . . . . . . . . . . . . 140ns * Low Charge Injection * Upgrade from DG211, DG212 * TTL, CMOS Compatible * Single or Split Supply Operation * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Audio Switching * Battery Operated Systems * Data Acquisition * Hi-Rel Systems * Sample and Hold Circuits * Communication Systems
Pinout
DG444, DG445 (16 LD SOIC, TSSOP) TOP VIEW
IN1 D1 S1 VGND S4 D4 IN4 1 2 3 4 5 6 7 8 16 IN2 15 D2 14 S2 13 V+ 12 VL 11 S3 10 D3 9 IN3
* Automatic Test Equipment
Ordering Information
PART NUMBER DG444DY* DG444DYZ* (Note) DG444DVZ* (Note) DG445DY* DG445DYZ* (Note) DG445DVZ* (Note) PART TEMP. MARKING RANGE (C) DG444DY DG444DYZ DG444DVZ DG445DY DG445DYZ DG445DVZ -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 16 Ld SOIC 16 Ld SOIC (Pb-free) PKG. DWG. # M16.15 M16.15
16 Ld TSSOP M16.173 (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) M16.15 M16.15
16 Ld TSSOP M16.173 (Pb-free)
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 1999, 2003, 2004, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
DG444, DG445 Functional Diagrams
DG444
S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4 IN4 D4 SWITCHES SHOWN FOR LOGIC "1" INPUT IN4 D4 IN3 D3 S4 IN2 D2 S3 IN1 D1 S2
Pin Descriptions
DG445
S1
PIN 1 2 3 4 5 6 7 8 9 10 11 12
SYMBOL IN1 D1 S1 VGND S4 D4 IN4 IN3 D3 S3 VL V+ S2 D2 IN2
DESCRIPTION Logic Control for Switch 1 Drain (Output) Terminal for Switch 1 Source (Input) Terminal for Switch 1 Negative Power Supply Terminal Ground Terminal (Logic Common) Source (Input) Terminal for Switch 4 Drain (Output) Terminal for Switch 4 Logic Control for Switch 4 Logic Control for Switch 3 Drain (Output) Terminal for Switch 3 Source (Input) Terminal for Switch 3 Logic Reference Voltage Positive Power Supply Terminal (Substrate) Source (Input) Terminal for Switch 2 Drain (Output) Terminal for Switch 2 Logic Control for Switch 2
TRUTH TABLE LOGIC 0 1 VIN 0.8V 2.4V DG444 ON OFF DG445
13 14 OFF 15 ON 16
Schematic Diagram
V+
(One Channel)
S VL VV+ INX
D
GND
V-
2
FN3586.10 June 4, 2007
DG444, DG445
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) + 0.3V Digital Inputs, VS , VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Packages). . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V (Max) Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max) Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min) Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on SX , DX , or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 4) (NOTE 5) (NOTE 4) MIN TYP MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF DG444 DG445 Charge Injection, Q (Figure 2) OFF Isolation (Figure 4) Crosstalk (Channel-to-Channel) (Figure 3) Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current VIN Low, IIL Input Current VIN High, IIH ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) Source OFF Leakage Current, IS(OFF)
RL = 1k, CL = 35pF, VS = 10V (Figure 1)
+25
-
120
250
ns
+25 +25 CL = 1nF, VG = 0V, RG = 0 RL = 50, CL = 5pF, f = 1MHz +25 +25 +25 f = 1MHz, VANALOG = 0 (Figure 5) +25 +25 +25
-
110 160 -1 60 -100 4 4 16
140 210 -
ns ns pC dB dB pF pF pF
VIN Under Test = 0.8V, All Others = 2.4V VIN Under Test = 2.4V, All Others = 0.8V
Full Full
-0.5 -0.5
-0.00001 0.00001
0.5 0.5
A A
Full IS = 10mA, VD = 8.5V, V+ = 13.5V, V- = -13.5V V+ = 16.5V, V- = -16.5V, VD = 15.5V, VS = 15.5V +25 Full +25 +85
-15 -0.5 -5
50 0.01 -
15 85 100 0.5 5
V nA nA
3
FN3586.10 June 4, 2007
DG444, DG445
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 16.5V, V- = -16.5V, VD = 15.5V, VS = 15.5V TEMP (C) +25 +85 Channel ON Leakage Current, ID(ON) + IS(ON) POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V +25 +85 +25 +85 Logic Supply Current, IL +25 +85 Ground Current, IGND +25 +85 -1 -5 -1 -5 0.001 -0.0001 0.001 -0.001 1 5 1 5 A A A A A A A A V+ = 16.5V, V- = -16.5V, VS = VD , = 15.5V +25 +85 (NOTE 4) (NOTE 5) (NOTE 4) MIN TYP MAX -0.5 -5 -0.5 -10 0.01 0.08 0.5 5 0.5 10 UNITS nA nA nA nA
PARAMETER Drain OFF Leakage Current, ID(OFF)
Negative Supply Current, I-
Electrical Specifications
(Single Supply) Test Conditions: V+ = 12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q (Figure 2) ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON)
RL = 1k, CL = 35pF, VS = 8V (Figure 1) CL = 1nF, VG = 6V, RG = 0
+25 +25 +25
-
300 60 2
450 200 -
ns ns pC
Full IS = -10mA, VD = 3V, 8V V+ = 10.8V, VL = 5.25V +25 Full
0 -
100 -
12 160 200
V
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13.2V, VIN = 0V or 5V, VL = 5.25V +25 Full +25 Full Logic Supply Current, IL +25 Full Ground Current, IGND +25 Full NOTES: 3. VIN = input voltage to perform proper function. 4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. -1 -5 -1 -5 0.001 -0.0001 0.001 -0.001 1 5 1 5 A A A A A A A A
Negative Supply Current, I-
4
FN3586.10 June 4, 2007
DG444, DG445 Test Circuits and Waveforms
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform.
3V LOGIC INPUT 50% 0V tOFF SWITCH INPUT VS VO SWITCH OUTPUT 0V tON 80% 80% LOGIC INPUT 3V tr < 20ns tf < 20ns SWITCH INPUT S1 IN1 RL GND VCL VL V+ D1
VO
NOTE: Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS
Repeat test for Channels 2, 3 and 4. For load conditions, see Specifications. CL includes fixture and stray capacitance. RL V O = V S ----------------------------------R L + r DS ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
SWITCH OUTPUT
VO
VL RG
V+ D1 VO
INX (DG444)
OFF
ON
OFF
VG V-
CL
INX (DG445)
OFF
ON Q = VO x CL
VIN = 3V OFF GND
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+ C
+15V C V+
+15V
SIGNAL GENERATOR 10dBm
VS
VD
50
SIGNAL GENERATOR 10dBm
VS
0V, 2.4V
IN1
IN2
0V, 2.4V VD RL
INX
0V, 2.4V
ANALYZER RL
VD C GND V-15V
NC
ANALYZER
GND
V-
C
-15V
FIGURE 3. CROSSTALK TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
5
FN3586.10 June 4, 2007
DG444, DG445 Test Circuits and Waveforms
(Continued)
+15V C V+
VS INX IMPEDANCE ANALYZER VD f = 1MHz 0V, 2.4V
GND
V-15V
C
FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Application Information
FET INPUT OP AMP 3 2 +5V 12 2 GAIN1 AV = 1 GAIN2 AV = 10 GAIN3 AV = 20 GAIN4 AV = 100 1 15 16 10 9 7 8 DG444 OR DG445 VGND 4 -15V 5 6 R4 1k 11 R3 4k 14 GND VR2 5k VL +15V +
VIN
-
7 6 4 +15V -15V 13 V+ 3
VOUT
+5V VL +15V +5V
+15V V+ +15V VOUT 10k
1/ DG444 4
R1 90k
0V
0V
VIN
FIGURE 7. LEVEL SHIFTER
GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE, OP AMP OFFSET AND CMRR WILL LIMIT ACCURACY OF CIRCUIT
R1 + R2 + R3 + R4 V OUT --------------- = ------------------------------------------------ = 100 R4 V IN
WITH SW4 CLOSED
FIGURE 6. PRECISION WEIGHTED RESISTOR PROGRAMMABLE GAIN AMPLIFIER
6
FN3586.10 June 4, 2007
DG444, DG445 Typical Performance Curves
105 4 104 103 IL , I+, I-, IGND (nA) 3 VIN (V) 102 10 -(I-) 1 0.1 0.01 0 0 4 8 12 SUPPLY VOLTAGE (V) 16 20 0.001 -55 IL 0 50 TEMPERATURE (C) 100 125 I+, IGND
2 VL = 5V 1
VL = 7V
FIGURE 8. SWITCHING THRESHOLD vs SUPPLY VOLTAGE
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
105 104 103 rDS(ON) () IIN (pA) 102
80 70 60 50 40 30 20 0C -40C +85C +25C V+ = +15V V- = -15V
10
1 10 0.1 -55 0 50 TEMPERATURE (C) 100 125 0 -15
0 VD (V)
15
FIGURE 10. INPUT CURRENT vs TEMPERATURE
FIGURE 11. rDS(ON) vs VD AND TEMPERATURE
140 120 100 80 (dB) 60 40 OFF ISOLATION CROSSTALK
50 40 30 20 Q (pC) 10 0 -10 CL = 10nF V+ = +15V V- = -15V
CL = 1nF
20 0 100
V+ = +15V V- = -15V PGEN = 10dBm 1k 10k 100k 1M 10M
-20 -30 -10
FREQUENCY (Hz)
0 VS (V)
10
FIGURE 12. CROSSTALK REJECTION AND OFF ISOLATION vs FREQUENCY
FIGURE 13. CHARGE INJECTION vs SOURCE VOLTAGE
7
FN3586.10 June 4, 2007
DG444, DG445 Typical Performance Curves
25 V+ = +15V V- = -15V 20 CS(ON) + CD(ON) CS , D (pF) IS , ID (pA) 15 0
(Continued)
20 IS(OFF) , ID(OFF)
-20
-40
IS(ON) + ID(ON)
10
-60 5 CS(OFF) , CD(OFF) -80 V+ = +15V V- = -15V FOR I(OFF) , VD = -VS
0 -15
-10
-5
0 VA (V)
5
10
15
-100 -15
-10
-5
0 VS , VD (V)
5
10
15
FIGURE 14. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE
160 V+ = +15V V- = -15V 140 120 tON
FIGURE 15. LEAKAGE CURRENTS vs ANALOG VOLTAGE
150 V+ = +15V, V- = -15V VL = 5V
100 tON, tOFF (ns) 100 80 60 40 20 2 3 VIN (V) 4 5 0 2 3 VIN (V) 4 5 tOFF tON, tOFF (ns) tON
tOFF 50
FIGURE 16. SWITCHING TIME vs INPUT VOLTAGE (DG444)
160 140 tON 120 tON, tOFF (ns) 100 80 60 40 20 10 12 14 16 18 SUPPLY VOLTAGE (V) 20 22
FIGURE 17. SWITCHING TIME vs INPUT VOLTAGE (DG445)
160 VL = 5V 140 120 tON, tOFF (ns) 100 80 60 40 20 10 12 14 16 18 20 22 SUPPLY VOLTAGE (V) tON tOFF
tOFF
FIGURE 18. SWITCHING TIME vs POWER SUPPLY VOLTAGE (DG444)
FIGURE 19. SWITCHING TIME vs POWER SUPPLY VOLTAGE (DG445)
8
FN3586.10 June 4, 2007
DG444, DG445 Typical Performance Curves
400 V+ = +12V, V- = 0V VL = 5V 300 tON, tOFF (ns) tON, tOFF (ns) tON 400 tON (444) 300 tON (445) 200
(Continued)
500 V- = 0V, VL = 5V
200
100
tOFF
100
tOFF (445)
tOFF (444)
0 2 3 VIN (V) 4 5
0 8 10 12 14 16 18 POSITIVE SUPPLY (V) 20 22
FIGURE 20. SWITCHING TIME vs INPUT VOLTAGE (DG444) (SINGLE 12V SUPPLY)
30 V+ = 12V V- = 0V
FIGURE 21. SWITCHING TIMES vs SINGLE SUPPLY VOLTAGE
10 IS(OFF) , ID(OFF) 0
20
-10 10 CL = 10nF CL = 1nF 0 -30 IS , ID (pA) Q (pC)
-20 IS(ON) + ID(ON) V+ = +12V V- = 0V FOR ID , VS = 0 FOR IS, VD = 0
-10 0 4 VS (V) 8
-40 0 6 VS , VD (V) 12
FIGURE 22. CHARGE INJECTION vs SOURCE VOLTAGE (SINGLE 12V SUPPLY)
20 V+ = +12V V- = 0V
FIGURE 23. SOURCE/DRAIN LEAKAGE CURRENTS (SINGLE 12V SUPPLY)
CS(ON) + CD(ON) 15
CS , D (pF)
10
5
CS(OFF) , CD(OFF)
0 0 6 VA (V) 12
FIGURE 24. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY)
9
FN3586.10 June 4, 2007
DG444, DG445 Die Characteristics
METALLIZATION: Type: SiAl Thickness: 12kA 1kA PASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG444, DG445
D1 (2) IN1 (1) IN2 (16)
(15) D2
S1 (3)
(14) S2
V- (4)
(13) V+ SUBSTRATE
GND (5)
(12) VL
S4 (6)
(11) S3
(7) D4
(8) IN4
(9) IN3
(10) D3
10
FN3586.10 June 4, 2007
DG444, DG445 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D E1
A2 c 0.10(0.004) C AM BS
MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 6.25 0.50 16 8o 0o 8o MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 6.50 0.70 NOTES 9 3 4 6 7 Rev. 1 2/02
MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 0.246 0.020 16 0o
MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 0.256 0.028
A1
e
b 0.10(0.004) M
e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
11
FN3586.10 June 4, 2007
DG444, DG445 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 16 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN3586.10 June 4, 2007

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